Ethernet PCI Card, Internal

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PCI Express, which is abbreviated officially with PCIe (also PCI-E is often used) and should not be mistaken for PCI-X, is an implementation of the PCI connection standard that uses existing PCI programming concepts, but bases it on a completely different and much faster full duplex, multi-lane, point to point serial physical-layer communications protocol. PCI Express was formerly known as Arapaho or 3GIO for 3rd Generation I/O.

PCIe transfers data at 250 MB/s per lane. With a maximum of 32 lanes, PCIe allows for a total combined transfer rate of 8 GB/s. To put these figures into perspective, a single lane has nearly twice the data rate of normal PCI, a four lane slot has a comparable data rate to the fastest version of PCI-X, and an eight lane slot has a data rate comparable to the fastest version of AGP. The full duplex point to point nature of PCIe should further improve its advantage over PCI, particularly in systems with many devices.

Overview

The PCIe physical layer consists of a network of serial interconnects much like twisted pair ethernet. A single hub with many pins on the mainboard is used, allowing extensive switching and parallelism. This design was chosen because as clock rates increase, synchronization of parallel connections is hindered by timing skew. PCIe is just one example of a general trend away from parallel buses to serial interconnects. For other examples, see HyperTransport, Serial ATA, USB, SAS or FireWire.

PCIe is supported primarily by Intel, which started working on the standard as the Arapahoe project after pulling out of the InfiniBand system.

PCIe is intended to be used as a local interconnect only. As it is based on the existing PCI system, cards and systems can be converted to PCI Express by changing the physical layer only — existing systems could be adapted to PCI Express without any change in software. The increased bandwidth on PCI Express allows it to replace almost all existing internal buses, including AGP and PCI, and Intel envisions a single PCI Express controller talking to all external devices, as opposed to the northbridge/southbridge solution in current machines.

Hardware protocol summary

The PCIe link is built around dedicated unidirectional couples of serial (1-bit), point-to-point connection known as a "lane". This is in sharp contrast to the PCI connection, which is a bus-based system where all the devices share the same bidirectional, 32-bit (or 64-bit), parallel bus.

PCI Express is a layered protocol, consisting of a Transaction Layer, a Data Link Layer, and a Physical Layer. The Physical Layer is further divided into a logical sublayer and an electrical sublayer. The logical sublayer is frequently further divided into a Physical Coding Sublayer (PCS) and a Media Access Control (MAC) sublayer (terms borrowed from the IEEE 802 model of networking protocol).

Read more at Wikipedia.org